The present invention relates to interfaces between test and application equipments.
IC testers generate dedicated analog and/or digital signals that are supplied to a device under test (DUT) for analyzing the response thereof. Such testers are described in detail e.g. in the co-pending European Patent application No. 99105625.0 by the same applicant, EP-A-882991, U.S. Pat. No. 5,499,248, or U.S. Pat. No. 5,453,995.
In most cases, the provision of signals from the tester to a specific application site of the DUT has to be matched with the specific mechanical and electrical properties of the tester as well as of an application equipment handling the DUT.
FIG. 1 shows an example of a typical DUT application equipment such as a wafer prober 10 for transporting and positioning highly sensitive silicon wafers as DUTs. The wafers (not visible inside the wafer prober 10) are internally connected to a probe card 20 as interface of the wafer prober 10 towards a tester 25 (in FIG. 1 only symbolized as a general block). Wafer probers are generally applied for testing integrated circuit in the earliest possible production phase.
The probe card 20 is typically a device-specific printed circuit board (PCB), e.g. with high-density contact needles on the wafer side and gold-plated contact pads on the tester side (as the side visible in FIG. 1). The probe card 20 normally straddles the dense (needle) pattern form the wafer side to a wider pad pattern for contacting with the tester 25. The size of the probe card 20 is generally limited by the hardware of the wafer prober 10. The wafer prober 10 has to ensure a reliable electrical contact between the contact pads of the wafer and the probe card 20.
A DUT board 30 represents the electrical and mechanical interface of the tester 25 towards the DUT. The DUT board 30 normally is a device specific printed circuit board (PCB) custom-built for the specific requirements of the DUT application equipment and can be exchanged dependent on the respective application. More details about the DUT boards 30 are described in particular in the aforementioned co-pending European Patent Application No. 99105625.0. In case that the DUT board 30 is provided as a custom-built exchangeable part, the DUT board 30 is often contacted within the tester 25 by means of spring-loaded contact pins (also called xe2x80x9cPogo(trademark)xe2x80x9d)
While the DUT board 30 and the probe card 20 are electrically optimized (e.g. with respect to signal speed, signal purity, impedance, and transmission rate) regarding either the tester 25 or the DUT of the wafer prober 10, a good electrical and mechanical matching between the DUT board 30 and the probe card 20 has to be achieved. This becomes in particular important with increasing signal transmission rates going up to two Gigabit per second.
In the example of FIG. 1, an interface tower 50 (also called xe2x80x9cPogo(trademark) towerxe2x80x9d ) is used as interface between the DUT board 30 and the probe card 20. The interface tower 50 converts the pin pattern (normally rectangular arrangement) of the DUT board 30 of the tester 25 to the pattern (normally round and more dense) of the probe card 20. In the example of FIG. 1, the interface tower 50 further has to bring signals from the tester 25 through a round-shaped hole in a head plate 60 of the wafer prober 10 and bridge the spatial distance between the DUT board 30 and the probe card 20.
All the interfacing provided by the interface tower 50 has to be done with a minimum loss in performance for the entire test system provided by the tester 25 and the application equipment of the wafer prober 10. That means that all parts in the electrical path of the interface tower 50 have to maintain a controlled impedance (normally 50 xcexa9) and a high contact quality for each provided tester channel (e.g. more than 1000 channels).
FIG. 2A shows in cross sectional view an embodiment of the interface tower 50 (product number E7017AA) as used for the Hewlett-Packard HP 83000. The interface tower 50 is of cylindrical shape with a central aperture 100. A solid aluminum core 110 bears the electrical and mechanical contacts. The core 110 comprises a plurality of signal paths 120 and ground contacts 130. In the representation of FIG. 2A, the top side of the tower interface 50 is to be directed towards the DUT board 30, while the lower side of the interface tower 50 is to be directed to and to be contact with the probe card 20.
FIG. 2B shows in greater detail the electrical paths of the interface tower 50 as depicted on the left side of FIG. 2A. Each signal path 120 is provided by a double-sided spring-loaded contact (Pogo(trademark)) isolated by air within holes 140 drilled through the core 110. Ground connection is performed by the ground contacts 130 provided by single-sided ground Pogos, which are arranged around the signal paths 120 and contacted directly with the aluminum core 110. This arrangement of the ground contacts 130 together with the air-isolated holes 140 generates a 50 xcexa9 environment, when a defined relation between the diameters of the electrical contacts of the signal paths 120 and the holes 140 is selected. Thus, the core 110 of the interface tower 50 provides a solid ground for all tester signals transmitted via the signal paths 120 and has to be isolated from a mechanical ground to avoid ground loops in the interface tower 50.
The tower interface 50, as shown in FIG. 2A, provides an excellent transmission of electrical signals between the DUT board 30 and the probe card 20. The electrical configuration of the signal paths 120 and the ground contacts 130 ensures an almost loss-free signal transmission, even for very high transmission rates with bandwidths in the range of up to 7 GHz.
The provision of the holes 140 with a defined diameter over the entire length of the holes 140, however, encounters severe mechanical difficulties. In case of the above described interface tower 50 with the product number E7017AA, holes 140 have to be provided with a diameter of 3 mm over a length of 50 mm. It is clear for the skilled person in the art that the provision of such holes is extremely difficult and costly and renders the interface tower 50 to be relatively costly. In this context, it has to be understood that each interface tower 50 normally is a specific custom-built part and usually only covers one specific pin-count (e.g. the number of individual electrical paths to be provided) for one specific tester arrangement. While, on one hand, the price of each interface tower 50 is relatively high (e.g. in the range of $ 30,000), a failure or breakdown of the interface tower 50, on the other hand, can lead to significant costs until the testing procedure can be resumed. Thus, it will be required to keep relatively costly spare interface towers 50 in stock to reduce possible test stoppage times.
It is therefore an object of the present invention to provide a lower cost interface between test and application equipment. The object is solved by the independent claims. Preferred embodiments are shown by the dependent claims.
According to the invention, an interface between test and application equipment (also referred to as tester/application interface or TA-interface) is provided with individual modular and exchangeable segments, i.e., structures. Each segment can comprise one or more electrical signal and/or ground paths or simply be a dummy segment in order to fill unused segment space with the TA-interface.
The modular arrangement of the segments allows to significantly reduce the testing costs, since the TA-interface, on one hand, can easily be adapted to a specific pin-count in a respective application. On the other hand, broken or malfunctioning segments can easily be exchanged without requiring to exchange the entire TA-interface. The TA-interface can thus be configured in accordance with the actual requirements and might also be upgraded on demand, thus allowing to distribute or shift costs until the actual moment of requirement. Furthermore, the modular segment configuration allows to limit stock costs from entire TA-interfaces to only less costly segments, in order to limit unavoidable stoppage time of the testing procedure.
In a preferred embodiment, all segments are substantially equal. In another embodiment, the TA-interface only comprises one or more different types of segments, whereby the segments of each type are equal. This further allows reducing costs due to an increased standardization and exchangeability within the segments of the same type.
In a further embodiment, one or more of the segments are electrically insulated or isolated, so that each of those one or more segments can be provided to be electrically independent with an individual electrical characteristics, such as an individual ground condition. This is in particular useful for testing DUTs with mixed analog and digital functionality.
In one embodiment, the ground condition of one or more of the electrically independent segments can be configured independently.
The invention thus provides a modular product structure allowing customer-specific configurations with lower price for lower pin-counts and rendering on site repair/exchange of segments (e.g. by the customer) possible. The invention further allows to provide segments with separated ground conditions, thus significantly increasing the flexibility of the entire test system and enabling testing of applications with mixed functionality (e.g. digital and analog).
In most cases, the TA-interface according to the invention is fully compatible with TA-interfaces already commercially available, such as within the Hewlett-Packard HP 83000 system.
In general, the TA-interface is applied for providing an electromagnetic link between test and application equipment. In most cases, however, the electromagnetic link is an electrical contact, an optical contact, or a combination of both. The test equipment preferably is an integrated circuit tester, and, accordingly, the application equipment preferably is an integrated circuit handling equipment.